https://learning.intel.com/Developer/learn/course/external/view/elearning/76/using-the-10gb-ethernet-design-examples https://learning.intel.com/Developer/learn/course/external/view/elearning/77/introduction-to-the-low-latency-10gb-ethernet-mac-intelr-fpga-ip-core https://learning.intel.com/Developer/learn/course/external/view/elearning/78/introduction-to-the-10gb-ethernet-phy-intelr-fpga-ip-cores https://learning.intel.com/Developer/learn/course/external/view/elearning/79/low-density-parity-check-ldpc-codes-intelr-fpga-ip-for-5g-systems https://learning.intel.com/Developer/learn/course/external/view/elearning/89/external-memory-interfaces-in-agilex-fpgas-part-1-introduction https://learning.intel.com/Developer/learn/course/external/view/elearning/90/external-memory-interfaces-in-agilex-fpgas-part-2-implementation https://learning.intel.com/Developer/learn/course/external/view/elearning/91/external-memory-interfaces-in-agilex-fpgas-part-3-verification https://learning.intel.com/Developer/learn/course/external/view/elearning/92/external-memory-interfaces-in-agilex-fpgas-part-4-on-chip-debugging https://learning.intel.com/Developer/learn/course/external/view/elearning/93/advanced-system-design-using-platform-designer-hierarchical-system-design https://learning.intel.com/Developer/learn/course/external/view/elearning/94/advanced-system-design-using-platform-designer-system-optimization https://learning.intel.com/Developer/learn/course/external/view/elearning/95/advanced-system-design-using-platform-designer-component-system-simulation https://learning.intel.com/Developer/learn/course/external/view/elearning/96/advanced-system-design-using-platform-designer-system-verification-with-system-console https://learning.intel.com/Developer/learn/course/external/view/elearning/97/avalon-verification-suite https://learning.intel.com/Developer/learn/course/external/view/elearning/98/design-block-reuse-in-the-intelr-quartusr-prime-pro-software https://learning.intel.com/Developer/learn/course/external/view/elearning/99/fast-easy-io-system-design-with-interface-planner https://learning.intel.com/Developer/learn/course/external/view/elearning/105/avalon-yan-zheng-tao-zhuang https://learning.intel.com/Developer/learn/course/external/view/elearning/108/stratixr-10-qi-jian-pei-zhi https://learning.intel.com/Developer/learn/course/external/view/elearning/109/intel-fpga-qi-jian-de-pei-zhi-fang-an https://learning.intel.com/Developer/learn/course/external/view/elearning/111/yue-shu-yuan-tong-bu-jie-kou https://learning.intel.com/Developer/learn/course/external/view/elearning/112/yue-shu-shuang-bei-shu-ju-su-lu-yuan-tong-bu-jie-kou https://learning.intel.com/Developer/learn/course/external/view/elearning/113/pei-zhialtera-fpga-de-jie-shao https://learning.intel.com/Developer/learn/course/external/view/elearning/116/cai-yongdsp-builder-gao-ji-mo-kuai-ku-jin-xing-she-ji-jian-jie https://learning.intel.com/Developer/learn/course/external/view/elearning/119/ru-he-kai-shi-yi-ge-jian-dan-defpga-she-ji https://learning.intel.com/Developer/learn/course/external/view/elearning/120/shi-yongquartus-prime-ruan-jian-gong-ju-jian-jie https://learning.intel.com/Developer/learn/course/external/view/elearning/126/jian-jin-shi-bian-yi-ru-men https://learning.intel.com/Developer/learn/course/external/view/elearning/127/quartus-ii-ruan-jian-tcl-jiao-ben https://learning.intel.com/Developer/learn/course/external/view/elearning/136/vhdl-ji-chu https://learning.intel.com/Developer/learn/course/external/view/elearning/137/verilog-hdl-ji-chu https://learning.intel.com/Developer/learn/course/external/view/elearning/138/systemverilog-hequartus-ii-ruan-jian https://learning.intel.com/Developer/learn/course/external/view/elearning/142/shi-yongaltera-fpga-zhong-de-gao-xing-neng-cun-chu-qi-jie-kou https://learning.intel.com/Developer/learn/course/external/view/elearning/143/di10dai-qi-jian-nei-cun-jie-kouip-jie-shao-part-1 https://learning.intel.com/Developer/learn/course/external/view/elearning/144/di10dai-qi-jian-ji-cheng-de-nei-cun-jie-kouip-part-2 https://learning.intel.com/Developer/learn/course/external/view/elearning/145/di10dai-qi-jian-nei-cun-jie-kouip-yan-zheng-part-3 https://learning.intel.com/Developer/learn/course/external/view/elearning/146/di10dai-qi-jian-nei-cun-jie-kouip-de-pian-nei-diao-shi-part-4 https://learning.intel.com/Developer/learn/course/external/view/elearning/147/agilex-7-agilex-5-fpgas-configuration https://learning.intel.com/Developer/learn/course/external/view/elearning/148/configuration-for-stratixr-10-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/149/configuration-schemes-for-intelr-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/151/yongopencl-zaifpga-shang-shi-xian-bing-xing-ji-suan https://learning.intel.com/Developer/learn/course/external/view/elearning/153/zaiintel-fpga-shang-yun-xingopencl https://learning.intel.com/Developer/learn/course/external/view/elearning/154/bu-fen-zhong-pei-zhi https://learning.intel.com/Developer/learn/course/external/view/elearning/155/intel-ping-tai-she-ji-gong-juplatform-designer-jian-jie https://learning.intel.com/Developer/learn/course/external/view/elearning/156/zhong-wen-ban-shi-yongavalon-heaxi-jie-kou-shi-xian-ding-zhiip-kai-fa https://learning.intel.com/Developer/learn/course/external/view/elearning/158/shi-yongplatform-designer-chuang-jian-xi-tong-she-ji-wan-cheng-xi-tong https://learning.intel.com/Developer/learn/course/external/view/elearning/160/intelr-stratixr-10-shou-fa-qi-ji-chu https://learning.intel.com/Developer/learn/course/external/view/elearning/161/stratixr-10-hyperflex-jie-gou-jie-shao https://learning.intel.com/Developer/learn/course/external/view/elearning/166/ji-yuarm-de-xin-pian-xi-tong-ying-jian-she-ji-liu-cheng https://learning.intel.com/Developer/learn/course/external/view/elearning/168/constraining-source-synchronous-interfaces https://learning.intel.com/Developer/learn/course/external/view/elearning/169/shou-fa-qi-gong-ju-bao https://learning.intel.com/Developer/learn/course/external/view/elearning/170/intelr-stratixr-10-qi-jian-de-san-re-guan-li https://learning.intel.com/Developer/learn/course/external/view/elearning/172/debugging-with-signal-tap-for-intelr-fpgas-office-hours https://learning.intel.com/Developer/learn/course/external/view/elearning/173/constraining-double-data-rate-source-synchronous-interfaces https://learning.intel.com/Developer/learn/course/external/view/elearning/174/introduction-to-configuring-intelr-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/175/using-the-generic-serial-flash-interface https://learning.intel.com/Developer/learn/course/external/view/elearning/176/debugging-jtag-chain-integrity https://learning.intel.com/Developer/learn/course/external/view/elearning/183/using-design-space-explorer https://learning.intel.com/Developer/learn/course/external/view/elearning/186/dsp-builder-advanced-blockset-interfaces-and-ip-libraries https://learning.intel.com/Developer/learn/course/external/view/elearning/187/dsp-builder-advanced-blockset-getting-started https://learning.intel.com/Developer/learn/course/external/view/elearning/188/dsp-builder-advanced-blockset-using-primitives https://learning.intel.com/Developer/learn/course/external/view/elearning/190/basics-of-programmable-logic-history-of-digital-logic-design https://learning.intel.com/Developer/learn/course/external/view/elearning/191/basics-of-programmable-logic-fpga-architecture https://learning.intel.com/Developer/learn/course/external/view/elearning/192/how-to-begin-a-simple-fpga-design https://learning.intel.com/Developer/learn/course/external/view/elearning/193/using-the-intelr-quartusr-prime-standard-edition-software-an-introduction https://learning.intel.com/Developer/learn/course/external/view/elearning/194/the-intelr-quartusr-prime-software-foundation-standard-edition-online-training https://learning.intel.com/Developer/learn/course/external/view/elearning/195/the-intelr-quartusr-prime-software-foundation-pro-edition-online-training https://learning.intel.com/Developer/learn/course/external/view/elearning/201/understanding-timing-analysis-in-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/202/introduction-to-incremental-compilation-in-the-intelr-quartusr-prime-standard-edition-software https://learning.intel.com/Developer/learn/course/external/view/elearning/203/signal-tap-logic-analyzer-introduction-getting-started https://learning.intel.com/Developer/learn/course/external/view/elearning/204/signal-tap-logic-analyzer-basic-configuration-trigger-conditions https://learning.intel.com/Developer/learn/course/external/view/elearning/205/signal-tap-logic-analyzer-state-based-triggering-compilation-programming https://learning.intel.com/Developer/learn/course/external/view/elearning/206/signal-tap-logic-analyzer-data-acquisition-additional-features https://learning.intel.com/Developer/learn/course/external/view/elearning/207/introduction-to-tcl https://learning.intel.com/Developer/learn/course/external/view/elearning/208/intelr-quartusr-prime-software-tcl-scripting https://learning.intel.com/Developer/learn/course/external/view/elearning/209/command-line-scripting https://learning.intel.com/Developer/learn/course/external/view/elearning/210/university-self-guided-lab-become-an-fpga-designer-in-4-hours https://learning.intel.com/Developer/learn/course/external/view/elearning/211/clock-domain-crossing-considerations https://learning.intel.com/Developer/learn/course/external/view/elearning/212/serdes-channel-simulation-with-ibis-ami-models https://learning.intel.com/Developer/learn/course/external/view/elearning/213/power-analysis https://learning.intel.com/Developer/learn/course/external/view/elearning/214/power-optimization https://learning.intel.com/Developer/learn/course/external/view/elearning/216/design-evaluation-for-timing-closure https://learning.intel.com/Developer/learn/course/external/view/elearning/217/the-niosr-ii-processor-hardware-abstraction-layer https://learning.intel.com/Developer/learn/course/external/view/elearning/218/cycloner-v-arriar-v-and-arriar10-soc-hardware-overview https://learning.intel.com/Developer/learn/course/external/view/elearning/222/agilex-7-soc-fpga-hard-processor-system-hps-overview https://learning.intel.com/Developer/learn/course/external/view/elearning/223/debugging-with-the-ethernet-toolkit https://learning.intel.com/Developer/learn/course/external/view/elearning/224/intelr-fpga-e-tile-clocking https://learning.intel.com/Developer/learn/course/external/view/elearning/225/reducing-compile-time-with-fast-preservation https://learning.intel.com/Developer/learn/course/external/view/elearning/228/generation-10-transceiver-clocking https://learning.intel.com/Developer/learn/course/external/view/elearning/229/building-a-generation-10-transceiver-phy-layer https://learning.intel.com/Developer/learn/course/external/view/elearning/230/getting-to-timing-closure-faster-office-hours https://learning.intel.com/Developer/learn/course/external/view/elearning/231/high-bandwidth-memory-in-altera-fpgas-part-2-hbm-controller-features https://learning.intel.com/Developer/learn/course/external/view/elearning/232/high-bandwidth-memory-in-altera-fpgas-part-3-implementation https://learning.intel.com/Developer/learn/course/external/view/elearning/233/high-bandwidth-memory-in-altera-fpgas-part-1-introduction https://learning.intel.com/Developer/learn/course/external/view/elearning/234/vhdl-basics https://learning.intel.com/Developer/learn/course/external/view/elearning/235/verilog-hdl-basics https://learning.intel.com/Developer/learn/course/external/view/elearning/236/systemverilog-with-quartusr-prime-design-software https://learning.intel.com/Developer/learn/course/external/view/elearning/237/best-design-practices-for-timing-closure https://learning.intel.com/Developer/learn/course/external/view/elearning/238/creating-high-performance-designs-in-intelr-stratixr-10-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/239/creating-high-performance-designs-in-20-nm-intelr-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/240/introduction-to-high-level-synthesis-part-1-of-7 https://learning.intel.com/Developer/learn/course/external/view/elearning/241/hls-interfaces-part-2-of-7 https://learning.intel.com/Developer/learn/course/external/view/elearning/242/hls-loop-optimizations-part-3-of-7 https://learning.intel.com/Developer/learn/course/external/view/elearning/243/hls-data-types-part-4-of-7 https://learning.intel.com/Developer/learn/course/external/view/elearning/244/hls-local-memory-optimizations-part-5-of-7 https://learning.intel.com/Developer/learn/course/external/view/elearning/245/hls-performance-optimization-part-6-of-7 https://learning.intel.com/Developer/learn/course/external/view/elearning/246/hls-optimization-example-matrix-decomposition-part-7-of-7 https://learning.intel.com/Developer/learn/course/external/view/elearning/247/hls-coding-optimizations-for-intelr-stratixr-10-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/248/introduction-to-hybrid-memory-cubes-with-altera-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/249/implementing-the-hybrid-memory-cube-controller-ip-in-an-altera-fpga https://learning.intel.com/Developer/learn/course/external/view/elearning/250/incremental-block-based-compilation-in-the-intel-quartusr-prime-pro-software-introduction https://learning.intel.com/Developer/learn/course/external/view/elearning/251/incremental-block-based-compilation-in-the-intel-quartusr-prime-pro-software-design-partitioning https://learning.intel.com/Developer/learn/course/external/view/elearning/252/incremental-block-based-compilation-in-the-intel-quartusr-prime-pro-software-timing-closure-tips https://learning.intel.com/Developer/learn/course/external/view/elearning/253/initial-design-review-for-arriar-10-soc-fpga-designs https://learning.intel.com/Developer/learn/course/external/view/elearning/254/incremental-optimization-with-the-intel-quartus-prime-pro-edition-software-legacy-course https://learning.intel.com/Developer/learn/course/external/view/elearning/260/creating-reusable-design-blocks-introduction-to-ip-reuse-with-the-intelr-quartusr-prime-software https://learning.intel.com/Developer/learn/course/external/view/elearning/261/creating-reusable-design-blocks-ip-design-implementation-with-the-intelr-quartusr-prime-software https://learning.intel.com/Developer/learn/course/external/view/elearning/262/creating-reusable-design-blocks-ip-integration-with-the-intelr-quartusr-prime-software https://learning.intel.com/Developer/learn/course/external/view/elearning/268/interur-agilexr-debaisu-xiangkeinteru-hyperflexakitekuchano-gai-yao https://learning.intel.com/Developer/learn/course/external/view/elearning/270/interur-agilexr-debaisunomemoriintafeisuno-gai-yao https://learning.intel.com/Developer/learn/course/external/view/elearning/271/interur-agilexr-debaisunomemoriintafeisuno-tong-he https://learning.intel.com/Developer/learn/course/external/view/elearning/272/interu-agilexr-debaisunomemoriintafeisuno-jian-zheng https://learning.intel.com/Developer/learn/course/external/view/elearning/273/stratixr-10-debaisunokonfigureshon-ji-neng https://learning.intel.com/Developer/learn/course/external/view/elearning/274/daburudetaretonososu-tong-qiintafesuni-duisuru-zhi-yue https://learning.intel.com/Developer/learn/course/external/view/elearning/277/puroguramabururojikkuno-ji-chu-dejitarurojikkudezainno-li-shi https://learning.intel.com/Developer/learn/course/external/view/elearning/278/puroguramabururojikkuno-ji-chu-fpga-akitekucha https://learning.intel.com/Developer/learn/course/external/view/elearning/279/hajimeteno-fpga-she-ji https://learning.intel.com/Developer/learn/course/external/view/elearning/280/ibis-ami-moderuwo-shi-yongshitaserdeschanerunoshimyureshon https://learning.intel.com/Developer/learn/course/external/view/elearning/281/soc-hadouea-gai-yao-pato1 https://learning.intel.com/Developer/learn/course/external/view/elearning/282/soc-hadouea-gai-yao-pato2 https://learning.intel.com/Developer/learn/course/external/view/elearning/283/jesd204b-megacore-ip-overview-legacy-course https://learning.intel.com/Developer/learn/course/external/view/elearning/286/quartus-ii-pafekutokosukonpairu https://learning.intel.com/Developer/learn/course/external/view/elearning/287/quartus-ii-pafekutokosudezain-ru-li https://learning.intel.com/Developer/learn/course/external/view/elearning/288/quartus-ii-pafekutokosuio-puranningu https://learning.intel.com/Developer/learn/course/external/view/elearning/289/quartus-ii-pafekutokosupuroguramingutokonfigyureshon https://learning.intel.com/Developer/learn/course/external/view/elearning/290/quartus-ii-pafekutokosu-she-dingtoasainmento https://learning.intel.com/Developer/learn/course/external/view/elearning/291/quartus-ii-kai-fasofutouea-ji-chu-biansutatogaido https://learning.intel.com/Developer/learn/course/external/view/elearning/292/vhdl-ji-chu-bian https://learning.intel.com/Developer/learn/course/external/view/elearning/294/interur-20-nm-fpgadebaisude-gao-xing-nengwo-shi-xiansuru-she-ji-shou-fa https://learning.intel.com/Developer/learn/course/external/view/elearning/296/interuquartusr-primepuroedishon-kai-fasofutoueadenoburokkubesunoinkurimentarukonpairu-ru-men https://learning.intel.com/Developer/learn/course/external/view/elearning/297/interuquartusr-primepuroedishon-kai-fasofutoueadenoburokkubesunoinkurimentarukonpairu-dezainpatishon https://learning.intel.com/Developer/learn/course/external/view/elearning/299/quartusr-prime-puroedishonsofutoueaga-ti-gongsuruinkurimentaru-zui-shi-hua-ji-neng https://learning.intel.com/Developer/learn/course/external/view/elearning/300/zai-li-yong-ke-nengnadezainburokkuno-sheng-cheng-fang-faipdezaintosono-shi-zhuang https://learning.intel.com/Developer/learn/course/external/view/elearning/301/zai-li-yong-ke-nengnadezainburokkuno-sheng-cheng-fang-faquartus-iisofutoueawo-shi-yongshitaipno-tong-he https://learning.intel.com/Developer/learn/course/external/view/elearning/302/max-10-debaisunorimotoshisutemuappuguredo-ji-neng https://learning.intel.com/Developer/learn/course/external/view/elearning/303/max-10-debaisunorimotoshisutemuappuguredo-ji-nengdezainfuro-demonsutoreshon https://learning.intel.com/Developer/learn/course/external/view/elearning/304/generation-10debaisunomemoriintafesu-dao-ru-bian https://learning.intel.com/Developer/learn/course/external/view/elearning/305/generation-10debaisuniokerumemoriintafesuipno-tong-he https://learning.intel.com/Developer/learn/course/external/view/elearning/306/generation-10debaisuniokerumemoriintafesuipno-jian-zheng https://learning.intel.com/Developer/learn/course/external/view/elearning/307/generation-10debaisuniokerumemoriintafesuipnoonchippudebaggu https://learning.intel.com/Developer/learn/course/external/view/elearning/308/quartus-prime-kai-fasofutoueaheno-yi-xing-fang-fa https://learning.intel.com/Developer/learn/course/external/view/elearning/309/nios-ii-sofutoueatsurutodezainfurono-gai-yao https://learning.intel.com/Developer/learn/course/external/view/elearning/312/opencl-wo-shi-yongshita-bing-liekonpyutingu-ru-men-bian https://learning.intel.com/Developer/learn/course/external/view/elearning/313/interur-fpga-xiangkeopencl-puroguramu-ji-shu-fang-fa https://learning.intel.com/Developer/learn/course/external/view/elearning/314/interur-fpga-xiangke-opencl-shi-xing-fang-fa https://learning.intel.com/Developer/learn/course/external/view/elearning/316/isanetto-xiangkeinterur-fpga-etairuhado-ipnokonfigureshon https://learning.intel.com/Developer/learn/course/external/view/elearning/317/interur-quartusr-prime-kai-fasofutoueapuroedishon-chip-plannerno-shi-yong-fang-fa https://learning.intel.com/Developer/learn/course/external/view/elearning/318/qsys-ji-chu-bian https://learning.intel.com/Developer/learn/course/external/view/elearning/319/avalonoyobiaxiintafesuwo-shi-yongshitakasutamukonponento-kai-fa https://learning.intel.com/Developer/learn/course/external/view/elearning/320/qsyswo-shi-yongshitashisutemudezainno-sheng-cheng-fang-fa https://learning.intel.com/Developer/learn/course/external/view/elearning/322/interur-stratixr-10-fpga-toranshiba-ji-chu-bian https://learning.intel.com/Developer/learn/course/external/view/elearning/324/stratixr-10-hyperflex-akitekuchano-gai-yao https://learning.intel.com/Developer/learn/course/external/view/elearning/326/interur-hyperflex-akitekuchaniokeru-fast-forward-compile-tsuruno-shi-yong-fang-fa https://learning.intel.com/Developer/learn/course/external/view/elearning/328/hyper-pipelining-ru-men-bian https://learning.intel.com/Developer/learn/course/external/view/elearning/329/hyper-retiming-ru-men-bian https://learning.intel.com/Developer/learn/course/external/view/elearning/331/arria-10-debaisuniokeru-seu-single-event-upset-no-huan-he-ji-fa https://learning.intel.com/Developer/learn/course/external/view/elearning/332/toranshibabeshikku https://learning.intel.com/Developer/learn/course/external/view/elearning/333/armbesusoc-xiangkehadoueadezainfuro https://learning.intel.com/Developer/learn/course/external/view/elearning/336/da-xue-sheng-xiangkewakushoppu-dejitaru-hui-lunosutatikkutaimingu-jie-xi-ru-men-japanese-univ-workshop-intro-to-static-timing https://learning.intel.com/Developer/learn/course/external/view/elearning/337/introduction-to-analog-to-digital-conversion-in-intelr-maxr-10-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/338/integrating-an-analog-to-digital-converter-in-intelr-maxr-10-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/339/using-the-adc-toolkit-in-intelr-maxr-10-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/340/using-the-max-10-user-flash-memory-with-the-nios-ii-processor https://learning.intel.com/Developer/learn/course/external/view/elearning/341/remote-system-upgrade-in-intelr-maxr-10-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/342/using-the-max-10-user-flash-memory https://learning.intel.com/Developer/learn/course/external/view/elearning/343/using-high-performance-memory-interfaces-in-altera-28-nm-and-40-nm-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/344/introduction-to-memory-interfaces-ip-in-intelr-fpga-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/345/integrating-memory-interfaces-ip-in-intelr-fpga-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/346/verifying-memory-interfaces-ip-in-intelr-fpga-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/347/on-chip-debugging-of-memory-interfaces-ip-in-intelr-fpga-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/348/migrating-to-the-intelr-quartusr-prime-pro-edition-software-legacy-course https://learning.intel.com/Developer/learn/course/external/view/elearning/349/whats-new-in-201 https://learning.intel.com/Developer/learn/course/external/view/elearning/350/the-niosr-ii-processor-booting https://learning.intel.com/Developer/learn/course/external/view/elearning/351/using-the-nios-ii-processor-custom-components-and-instructions https://learning.intel.com/Developer/learn/course/external/view/elearning/352/using-the-niosr-ii-processor-hardware-development https://learning.intel.com/Developer/learn/course/external/view/elearning/366/connecting-to-the-28-nm-hard-ip-for-pci-express https://learning.intel.com/Developer/learn/course/external/view/elearning/367/connecting-to-the-arria-10-hard-ip-for-pci-express https://learning.intel.com/Developer/learn/course/external/view/elearning/368/customizing-the-28-nm-hard-ip-for-pci-express https://learning.intel.com/Developer/learn/course/external/view/elearning/369/customizing-intelr-stratixr-10-intel-arriar-10-intel-cycloner-10-gx-fpga-hard-ip-for-pci-express https://learning.intel.com/Developer/learn/course/external/view/elearning/370/designing-with-the-28-nm-hard-ip-for-pci-express https://learning.intel.com/Developer/learn/course/external/view/elearning/371/designing-with-intelr-stratixr-10-intel-arriar-10-intel-cycloner-10-gx-hard-ip-for-pci-express https://learning.intel.com/Developer/learn/course/external/view/elearning/372/introduction-to-the-28-nm-hard-ip-for-pci-express https://learning.intel.com/Developer/learn/course/external/view/elearning/373/introduction-to-the-arria-10-hard-ip-for-pci-express https://learning.intel.com/Developer/learn/course/external/view/elearning/376/partial-reconfiguration-for-intel-fpga-devices-introduction-project-assignments https://learning.intel.com/Developer/learn/course/external/view/elearning/377/partial-reconfiguration-for-intel-fpga-devices-design-guidelines-host-requirements https://learning.intel.com/Developer/learn/course/external/view/elearning/378/partial-reconfiguration-for-intel-fpga-devices-pr-host-ip-implementations https://learning.intel.com/Developer/learn/course/external/view/elearning/379/partial-reconfiguration-for-intel-fpga-devices-output-files-demonstration https://learning.intel.com/Developer/learn/course/external/view/elearning/380/using-intelr-quartusr-prime-pro-software-chip-planner https://learning.intel.com/Developer/learn/course/external/view/elearning/381/introduction-to-the-intelr-fpga-p-tile https://learning.intel.com/Developer/learn/course/external/view/elearning/382/power-analysis-optimization-for-intel-arria-10-stratix-10-devices-intro-early-power-estimator https://learning.intel.com/Developer/learn/course/external/view/elearning/383/power-analysis-optimization-for-intel-arria-10-stratix-10-devices-power-analyzer https://learning.intel.com/Developer/learn/course/external/view/elearning/384/power-analysis-optimization-for-intel-arria-10-stratix-10-devices-optimization https://learning.intel.com/Developer/learn/course/external/view/elearning/385/power-analysis-optimization-for-intel-arria-10-stratix-10-devices-smartvoltage-id https://learning.intel.com/Developer/learn/course/external/view/elearning/386/alterar-fpga-power-and-thermal-calculator-for-altera-fpga-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/387/introduction-to-platform-designer https://learning.intel.com/Developer/learn/course/external/view/elearning/388/custom-ip-development-using-avalonr-and-arm-amba-axi-interfaces https://learning.intel.com/Developer/learn/course/external/view/elearning/389/creating-a-system-design-with-platform-designer-getting-started https://learning.intel.com/Developer/learn/course/external/view/elearning/390/creating-a-system-design-with-platform-designer-finish-the-system https://learning.intel.com/Developer/learn/course/external/view/elearning/391/platform-designer-in-the-intelr-quartusr-prime-pro-edition-software https://learning.intel.com/Developer/learn/course/external/view/elearning/392/reset-methodology https://learning.intel.com/Developer/learn/course/external/view/elearning/393/read-me-first https://learning.intel.com/Developer/learn/course/external/view/elearning/394/intelr-stratixr-10-fpga-l-and-h-tile-transceiver-basics https://learning.intel.com/Developer/learn/course/external/view/elearning/395/intelr-fpga-e-tile-transceiver-basics https://learning.intel.com/Developer/learn/course/external/view/elearning/396/alterar-hyperflexr-architecture-overview https://learning.intel.com/Developer/learn/course/external/view/elearning/397/alterar-hyperflex-fpga-architecture-design-analyzing-critical-chains https://learning.intel.com/Developer/learn/course/external/view/elearning/398/eliminating-barriers-to-hyper-retiming https://learning.intel.com/Developer/learn/course/external/view/elearning/399/using-fast-forward-compile-for-hyperflexr-architecture https://learning.intel.com/Developer/learn/course/external/view/elearning/401/configuring-the-intelr-fpga-e-tile-hard-ip-for-ethernet https://learning.intel.com/Developer/learn/course/external/view/elearning/402/introduction-to-hyper-optimization https://learning.intel.com/Developer/learn/course/external/view/elearning/403/introduction-to-hyper-pipelining https://learning.intel.com/Developer/learn/course/external/view/elearning/404/introduction-to-hyper-retiming https://learning.intel.com/Developer/learn/course/external/view/elearning/405/alterar-hyperflex-fpga-architecture-design-loop-optimization https://learning.intel.com/Developer/learn/course/external/view/elearning/407/hyper-optimization-techniques-shannons-decomposition https://learning.intel.com/Developer/learn/course/external/view/elearning/408/stratixr-10-soc-fpga-hardware-and-hps-overview https://learning.intel.com/Developer/learn/course/external/view/elearning/409/quartusr-prime-software-hyper-aware-design-flow https://learning.intel.com/Developer/learn/course/external/view/elearning/410/building-an-intelr-stratixr-10-fpga-transceiver-phy-layer https://learning.intel.com/Developer/learn/course/external/view/elearning/411/seu-mitigation-in-intelr-fpga-devices-fault-injection https://learning.intel.com/Developer/learn/course/external/view/elearning/412/seu-mitigation-in-intelr-fpga-devices-hierarchy-tagging https://learning.intel.com/Developer/learn/course/external/view/elearning/433/university-self-guided-lab-introduction-to-static-timing-analysis-of-digital-circuits https://learning.intel.com/Developer/learn/course/external/view/elearning/793/getting-started-with-software-design-flow-for-alterar-soc-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/794/intelr-soc-fpga-bare-metal-programming-and-hardware-libraries https://learning.intel.com/Developer/learn/course/external/view/elearning/795/getting-started-with-linux-os-for-alterar-soc-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/796/profiling-intelr-soc-fpgas-with-arm-streamline https://learning.intel.com/Developer/learn/course/external/view/elearning/797/secure-boot-with-arria-10-soc-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/798/building-bootloader-for-alterar-soc-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/799/using-the-intel-quartus-prime-pro-edition-synthesis-engine https://learning.intel.com/Developer/learn/course/external/view/elearning/800/transceiver-toolkit-for-28-nm-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/803/timing-closure-using-timing-analyzer-custom-reporting https://learning.intel.com/Developer/learn/course/external/view/elearning/804/thermal-management-in-intelr-stratixr-10-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/805/introduction-to-the-triple-speed-ethernet-fpga-ip https://learning.intel.com/Developer/learn/course/external/view/elearning/806/implementing-the-triple-speed-ethernet-fpga-ip https://learning.intel.com/Developer/learn/course/external/view/elearning/807/university-self-guided-lab-introduction-to-fpgas-and-the-intelr-quartusr-prime-software https://learning.intel.com/Developer/learn/course/external/view/elearning/808/university-self-guided-lab-embedded-niosr-processor-platform-designer https://learning.intel.com/Developer/learn/course/external/view/elearning/810/mitigating-single-event-upsets-in-intelr-arriar-10-and-intel-cycloner-10-gx-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/811/transceiver-basics-for-20-nm-and-28-nm-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/812/hardware-design-flow-for-alterar-soc-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/823/introduction-to-the-intel-distribution-of-openvino-toolkit https://learning.intel.com/Developer/learn/course/external/view/elearning/827/tcl-jiao-ben-yu-yan-ru-men https://learning.intel.com/Developer/learn/course/external/view/elearning/829/intelr-quartus-prime-software-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/elearning/830/interur-agilexrdebaisunomemoriintafeisunoonchippudebaggu https://learning.intel.com/Developer/learn/course/external/view/elearning/831/gao-su-bao-cunniyorukonpairu-shi-jianno-duan-suo https://learning.intel.com/Developer/learn/course/external/view/elearning/832/interu-fpga-debaisu-xiangkeinteru-fpga-power-and-thermal-calculator https://learning.intel.com/Developer/learn/course/external/view/elearning/833/interur-quartusr-primepuroedishon-kai-fasofutoueanopurattofomudezaina https://learning.intel.com/Developer/learn/course/external/view/elearning/834/using-linux-on-intelr-soc-fpgas-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/elearning/835/the-niosr-ii-processor-introduction-to-developing-software https://learning.intel.com/Developer/learn/course/external/view/elearning/836/platform-designer-standard-interfaces https://learning.intel.com/Developer/learn/course/external/view/elearning/837/platform-designer-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/elearning/838/intelr-quartusr-prime-pro-software-timing-analysis-part-3-clock-constraints https://learning.intel.com/Developer/learn/course/external/view/elearning/839/intelr-quartusr-prime-pro-software-timing-analysis-part-1-timing-analyzer https://learning.intel.com/Developer/learn/course/external/view/elearning/840/intelr-quartusr-prime-pro-software-timing-analysis-part-2-sdc-collections https://learning.intel.com/Developer/learn/course/external/view/elearning/841/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces https://learning.intel.com/Developer/learn/course/external/view/elearning/842/intelr-quartusr-prime-pro-software-timing-analysis-part-5-timing-exceptions https://learning.intel.com/Developer/learn/course/external/view/elearning/843/timing-closure-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/classroom/851/beginner-workshop-for-alterar-fpgas https://learning.intel.com/Developer/learn/course/external/view/classroom/853/using-alterar-soc-fpgas-an-introduction https://learning.intel.com/Developer/learn/course/external/view/classroom/854/using-alterar-soc-fpgas-configuration-and-booting https://learning.intel.com/Developer/learn/course/external/view/classroom/859/alterar-fpga-timing-closure-lecture https://learning.intel.com/Developer/learn/course/external/view/classroom/861/verilog-hdl-advanced https://learning.intel.com/Developer/learn/course/external/view/classroom/862/verilog-hdl-basics https://learning.intel.com/Developer/learn/course/external/view/classroom/863/using-quartusrsoftware https://learning.intel.com/Developer/learn/course/external/view/elearning/891/introduction-to-openvino-integration-with-tensorflow https://learning.intel.com/Developer/learn/course/external/view/elearning/893/fpga-business-fundamentals https://learning.intel.com/Developer/learn/course/external/view/elearning/899/ecpri-intelr-fpga-ip-getting-started https://learning.intel.com/Developer/learn/course/external/view/elearning/900/ecpri-intelr-fpga-ip-architecture-and-interfaces https://learning.intel.com/Developer/learn/course/external/view/elearning/901/signal-tap-embedded-logic-analyzer-ask-an-expert-november-2021 https://learning.intel.com/Developer/learn/course/external/view/elearning/902/ecpri-intelr-fpga-ip-customizing-the-ip https://learning.intel.com/Developer/learn/course/external/view/elearning/938/university-self-guided-lab-introduction-to-simulation-and-debug-of-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/946/openvino-execution-provider-for-onnx-runtime https://learning.intel.com/Developer/learn/course/external/view/elearning/953/niosr-v-processor-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/elearning/954/interur-fpgapuroguramaburuakuserareshonkado-pac-n3000xiangkeakuserareta-ji-nengyunittoafu-no-gou-zhu https://learning.intel.com/Developer/learn/course/external/view/elearning/955/dsp-builderadobansutoburokkusetto-ru-men-bian https://learning.intel.com/Developer/learn/course/external/view/classroom/968/using-oneapi-with-intelr-fpgas-workshop https://learning.intel.com/Developer/learn/course/external/view/elearning/971/kurokkudomeinkurosshinguno-kao-lu-shi-xiang-japanese-cdc-considerations https://learning.intel.com/Developer/learn/course/external/view/elearning/972/fan-yongshiriarufurasshuintafeisuno-shi-yong-japanese-using-the-generic-serial-flash-interface https://learning.intel.com/Developer/learn/course/external/view/elearning/973/isanettotsurukittoniyorudebaggujapanese-debugging-with-the-ethernet-toolkit https://learning.intel.com/Developer/learn/course/external/view/elearning/974/fpga-niokerutaimingu-jie-xino-li-jie-japanese-understanding-timing-analysis-in-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/976/hyper-optimization-ru-men-bian-japanese-introduction-to-hyper-optimization https://learning.intel.com/Developer/learn/course/external/view/elearning/977/interur-quartusr-prime-kai-fasofutouea-hyper-aware-dezainfuro https://learning.intel.com/Developer/learn/course/external/view/elearning/978/risettono-fang-fa-japanese-reset-methodology https://learning.intel.com/Developer/learn/course/external/view/classroom/982/introduction-to-platform-designer-building-systems https://learning.intel.com/Developer/learn/course/external/view/classroom/989/alterar-fpgas-timing-analysis-lecture https://learning.intel.com/Developer/learn/course/external/view/classroom/990/alterar-fpgas-timing-analysis-hands-on-labs https://learning.intel.com/Developer/learn/course/external/view/elearning/1021/intelr-stratixr-10qi-jianopencldai-ma-you-hua-chinese-opencl-coding-optimizations-for-intelr-stratixr-10-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/1023/intel-agilexr-qi-jian-zhong-de-cun-chu-qi-jie-kou-jie-shao-chinese-introduction-to-memory-interfaces-in-intel-agilexr-7-fpgas-f-i-series https://learning.intel.com/Developer/learn/course/external/view/elearning/1024/intel-agilexr-qi-jian-zhong-de-cun-chu-qi-jie-kou-yan-zheng-chinese-verifying-memory-interfaces-in-intel-agilexr-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/1025/intel-agilexr-qi-jian-zhong-de-cun-chu-qi-jie-kou-pian-shang-diao-shi-chinese-on-chip-debugging-of-memory-interfaces-in-intelr-agilexr-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/1064/signal-tap-luo-ji-fen-xi-qi-jie-shao-he-ru-men https://learning.intel.com/Developer/learn/course/external/view/classroom/1066/quartusr-prime-software-debug-tools-signal-tap https://learning.intel.com/Developer/learn/course/external/view/elearning/1074/introduction-to-the-intelr-fpga-r-tile https://learning.intel.com/Developer/learn/course/external/view/classroom/7777/alterar-fpga-timing-closure-hands-on-lab https://learning.intel.com/Developer/learn/course/external/view/elearning/8633/design-space-explorer-no-shi-yong https://learning.intel.com/Developer/learn/course/external/view/elearning/8634/purattofomudezainano-biao-zhunintafeisujapanese-pd-standard-interfaces https://learning.intel.com/Developer/learn/course/external/view/elearning/8638/interur-stratixr-10-debaisu-xiangketoranshibatsurukitto-japanese-transceiver-toolkit-for-intelr-stratixr-10-devices https://learning.intel.com/Developer/learn/course/external/view/elearning/8779/signal-tap-luo-ji-fen-xi-qi-ji-chu-pei-zhichu-fa-tiao-jian-chinese-signal-tap-logic-analyzer-basic-configuration-trigger-conditions https://learning.intel.com/Developer/learn/course/external/view/elearning/8826/introduction-to-optimizing-fpgas-with-the-intelr-oneapi-toolkits https://learning.intel.com/Developer/learn/course/external/view/elearning/8827/using-fpgas-with-the-intelr-oneapi-toolkits https://learning.intel.com/Developer/learn/course/external/view/elearning/8837/ddr5-memory-and-the-memory-interface-ip-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/elearning/8847/signal-tap-luo-ji-fen-xi-qi-ji-yu-zhuang-tai-de-chu-fa-bian-yi-he-bian-cheng-chinese-signal-tap-logic-analyzer-state-based-triggering-compilation-programming https://learning.intel.com/Developer/learn/course/external/view/elearning/9142/arm-development-studio-for-intel-soc-fpgas-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/elearning/9359/openvino-digital-courseware-for-educators https://learning.intel.com/Developer/learn/course/external/view/elearning/9434/using-linux-with-intelr-soc-fpgas-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/elearning/9692/using-oneapi-with-intelr-fpgas-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/classroom/11817/introduction-to-the-niosr-v-processor https://learning.intel.com/Developer/learn/course/external/view/elearning/11882/introduction-to-fpgas-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/elearning/11883/introduction-to-the-intelr-quartusr-prime-software-ask-an-expert https://learning.intel.com/Developer/learn/course/external/view/elearning/11934/interur-oneapi-tsurukittowo-shi-yongshiteno-fpga-no-huo-yong-using-fpgas-intelr-oneapi-toolkits-japanese https://learning.intel.com/Developer/learn/course/external/view/elearning/11998/introduction-to-the-fpga-ai-suite https://learning.intel.com/Developer/learn/course/external/view/elearning/12024/device-tree https://learning.intel.com/Developer/learn/course/external/view/elearning/12213/engineering-change-order-in-intelr-quartusr-prime-pro-software https://learning.intel.com/Developer/learn/course/external/view/elearning/13837/fpga-ai-suite-custom-models https://learning.intel.com/Developer/learn/course/external/view/elearning/14013/introduction-to-the-intelr-fpga-f-tile https://learning.intel.com/Developer/learn/course/external/view/classroom/14346/intelr-simicsr-simulator-for-intelr-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/14481/niosr-ii-to-niosr-v-processors-migration https://learning.intel.com/Developer/learn/course/external/view/elearning/14483/niosr-vg-processor-custom-instructions https://learning.intel.com/Developer/learn/course/external/view/elearning/14484/niosr-v-processors-overview https://learning.intel.com/Developer/learn/course/external/view/elearning/14485/niosr-v-processors-hardware-integration https://learning.intel.com/Developer/learn/course/external/view/elearning/14713/niosr-v-processors-booting https://learning.intel.com/Developer/learn/course/external/view/elearning/14714/niosr-v-software-development-flow-with-ashling-riscfree-ide-for-intelr-fpga https://learning.intel.com/Developer/learn/course/external/view/elearning/14945/intelr-quartusr-software-gui-introduction https://learning.intel.com/Developer/learn/course/external/view/elearning/14946/intelr-quartusr-software-design-entry https://learning.intel.com/Developer/learn/course/external/view/elearning/14947/intelr-quartusr-software-physical-layout https://learning.intel.com/Developer/learn/course/external/view/elearning/14948/intelr-quartusr-software-netlist-viewers-cross-probing https://learning.intel.com/Developer/learn/course/external/view/elearning/14949/intelr-quartusr-software-jtag-debugging-tools https://learning.intel.com/Developer/learn/course/external/view/elearning/14950/intelr-quartusr-software-introduction-to-scripting https://learning.intel.com/Developer/learn/course/external/view/elearning/15065/intelr-simicsr-simulator-for-intelr-fpgas-command-line-interface https://learning.intel.com/Developer/learn/course/external/view/elearning/15074/intelr-simicsr-simulator-for-intelr-fpgas-hardware-inspection https://learning.intel.com/Developer/learn/course/external/view/elearning/15499/zynq-ultrascale-amd-fpga-to-agilex-5-conversion-guide https://learning.intel.com/Developer/learn/course/external/view/elearning/15516/agilex-5-fpgas-hard-processor-subsystem-hps-overview https://learning.intel.com/Developer/learn/course/external/view/elearning/15518/cycloner-v-to-agilex-5-fpga-migration https://learning.intel.com/Developer/learn/course/external/view/elearning/15519/using-the-gts-ethernet-hard-ip https://learning.intel.com/Developer/learn/course/external/view/elearning/15520/using-the-gts-pcie-hard-ip https://learning.intel.com/Developer/learn/course/external/view/elearning/15523/alterar-hyperflexr-fpga-architecture-design-pre-computation https://learning.intel.com/Developer/learn/course/external/view/elearning/15524/quartusr-prime-pro-software-transceiver-toolkit https://learning.intel.com/Developer/learn/course/external/view/elearning/15525/agilex-5-and-agilex-3-gts-transceiver-basics https://learning.intel.com/Developer/learn/course/external/view/elearning/15526/software-flow-for-agilex-5-soc-fpga https://learning.intel.com/Developer/learn/course/external/view/elearning/15531/introduction-to-agilex-5-fpga-dsp-with-ai-tensor-block https://learning.intel.com/Developer/learn/course/external/view/elearning/15919/alterar-agilex-fpgas-network-on-chip-noc-overview-introduction https://learning.intel.com/Developer/learn/course/external/view/elearning/15920/alterar-agilex-fpgas-network-on-chip-noc-implementation-optimization https://learning.intel.com/Developer/learn/course/external/view/elearning/16088/using-intelr-simicsr-simulator-and-ashling-riscfree-ide-for-alterar-fpgas https://learning.intel.com/Developer/learn/course/external/view/elearning/16124/implementing-mipi-solutions-in-alterar-fpgas https://learning.intel.com/Developer/learn/public/learning_plan/view/57/intel-distribution-of-openvino-toolkit-foundations-2024 https://learning.intel.com/Developer/learn/public/learning_plan/view/77/edge-insights-for-industrial-foundations https://learning.intel.com/Developer/learn/public/learning_plan/view/82/openvino-toolkit-foundations-2024 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